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8-Mar-16

Product Details

/ Microarchitecture
Processor core
Core stepping B1 (SLBVC)
Manufacturing process 0.032 micron High-K metal gate process
Data width 64 bit
Number of cores 4
Floating Point Unit Integrated
Level 1 cache size 4 x 32 KB instruction caches
4 x 32 KB data caches
Level 2 cache size 4 x 256 KB
Level 3 cache size 12 MB
Multiprocessing Up to 2 processors
Features
MMX instruction set
SSE
SSE2
SSE3
Supplemental SSE3
SSE4.1
SSE4.2
AES instructions
EM64T technology
Execute Disable bit
Hyper-Threading technology
Virtualization technology
Trusted Execution Technology
Turbo Boost Technology
Low power features Enhanced SpeedStep technology ?
On-chip peripherals
Integrated 3-channel DDR3 SDRAM Memory controller
Quick Path Interconnect

Electrical/Thermal parameters
V core (V) 0.8 - 1.3
Thermal Design Power (W) 80

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